Steel is a microprocessor core that implements the RV32I and Zicsr instruction sets of the RISC-V specifications. It is designed to be easy to use and targeted for embedded systems projects.

Key features

  • Simple and easy to use
  • Implements the RV32I base instruction set + Zicsr extension + M-mode privileged architecture
  • 3 pipeline stages, single-issue
  • Hardware described in Verilog
  • Full documentation
  • Passed all RISC-V Compliance Suite tests for the RV32I and Zicsr instruction sets
  • 1.36 CoreMarks/MHz


Steel is distributed under the MIT License. The license text is reproduced in the LICENCE.md file. Read it carefully and make sure you understand its terms before using Steel in your projects.


Steel aims to be compliant with the following versions of the RISC-V specifications:

  • Base ISA RV32I version 2.1
  • Zicsr extension version 2.0
  • Machine ISA version 1.11

GitHub repo

Steel files and documentation are available at GitHub (github.com/rafaelcalcada/steel-core).